1. Field of the Invention
The present invention relates to a communication system of nodes, and a communication method. More specifically, the present invention relates to a communication system having a serial interface of real-time characteristic, a cycle master node used in the communication system, and a communication method.
2. Description of the Related Art
Recently, attention is paid to IEEE 1394 as a standard of a real-time, high-speed, high-function multimedia-compliant serial interface. The IEEE 1394 interface is used for connection with peripheral devices such as a digital video camera or a hard disk drive, required to transmit a large amount of data at high speed. The IEEE 1394 interface has a communication rate as high as 100 Mbit/sec to 800 Mbit/sec, and data is transferred in isochronous transfer or asynchronous transfer. The isochronous transfer is a transfer mode used for a serial interface such as a USB in addition the IEEE 1394 interface, particularly used for a peripheral device that requires real-time characteristics. In the isochronous transfer suited for the multimedia, data is transferred for a short transfer time allocated to each of the devices within a constant cycle time (125 μs according to the IEEE 1394). For this reason, even if an access has occurred suddenly, data can be transferred from a device to each of the other devices for the transfer time allocated to each device.
Referring to FIGS. 1 to 4, a conventional IEEE 1394-compliant communication system will be described.
FIG. 1 is a block diagram showing a configuration of a conventional device (node) connected to a serial bus through an IEEE 1394-compliant interface. Referring to FIG. 1, a cycle master 1230 of a serial bus control unit 120 manages and controls a cycle time of 125 μs and generates a cycle start signal used for transferring a cycle start packet C for every 125 μs. A cycle control circuit 1410 of a link layer 140 transfers the cycle start packet C onto a serial bus 160 through a physical layer 150 in response to the cycle start signal from the cycle master 1230. Thus, it becomes possible to carry out time manage or control for the entire serial bus 160.
The serial bus control unit 120 and a transaction layer 130 are controlled by an application/software driver 110. The serial bus control unit 120 includes a bus manager 1210, an isochronous resource manager (IRM) 1220, the cycle master 1230, and a node controller 1250. The serial bus control unit 120 provides a set of a protocol, a service, and an operation procedure for monitoring and controlling various layers of the serial bus 160. Depending on the node, the serial bus control unit 120 does not include the bus manager 1210 and the IRM 1220. In such a case, a different node can play roles of the bus manager 1210 and the IRM 1220. If the bus manager 1210 is not provided, the IRM 1220 is often carries out a part of functions of the bus manager 1210.
The bus manager 1210 includes a power supply control function, a function of optimizing performance of the serial bus 160, and a function of installing a topology map, a speed map or the like. The IRM 1220 manages resources for isochronous transmission. If the bus manager 1210 is not present on the serial bus 160, the IRM 1220 designates one of nodes as the cycle master 1230. The cycle master 1230 transfers a cycle start request signal to the cycle control circuit 1410 of the link layer 140 such that a cycle start packet is transferred for every 125 μs. The node controller 1250 functions to monitor a state (connection and utilization state) of the node.
The transaction layer 130 is one of IEEE 1394-compliant logic layers, and is a layer that defines request/response protocol and that includes read and write functions and a lock function among a protocol layer stack specified for the serial bus 160.
The link layer 140 is present between the transaction layer 130 and the physical layer 150, and serves as an interface for both of the transaction layer 130 and the physical layer 150. The link layer 140 carries out addressing, data verification, and data framing. The link layer 140 includes the cycle control circuit 1410 and a data transfer circuit 1420, and carries out an asynchronous subaction process and an isochronous subaction process. Services provided by the link layer 140 are roughly divided into four, i.e., packet transmission from a link requester to a link responder (Request), packet reception by the link responder (Indication), acknowledgement transmission by the link responder (Response), and acknowledgement reception by the link requester (Confirmation).
The cycle control circuit 1410 outputs the cycle start packet C to the serial bus 160 for every 125 μs in response to the cycle start request signal from the cycle master 1230. The data transfer circuit 1420 transfers packet data generated by an application to the physical layer 150.
The physical layer 150 includes a bus control circuit 1510 and a transmission & reception circuit 1520. The bus control circuit 1510 carries out arbitration in response to a request from the link layer 140, and guarantees that only one node can transmit data on the serial bus 160. The transmission & reception circuit 1520 transfers the packet data from the data transfer circuit 1420 to the serial bus 160. In case of the isochronous subaction, the transmission/reception circuit 1520 transfers the packet data to the serial bus 160 while securing a channel.
FIG. 2 is a conceptual diagram of a conventional communication system of nodes 1 to 3 connected to one another by a serial bus. For instance, A1 to A3 are added as symbols subsequent to a reference symbol I that denotes each of isochronous packets transmitted from nodes 1 to 3 in a cycle time N-A. Likewise, B1 to B3 and C1 to C3 are added as symbols subsequent to the reference symbol I that denotes each of isochronous packets transmitted from the nodes 1 to 3 in a cycle time N-B and a cycle time N-C, respectively. In addition, A1 to A3 are added as symbols subsequent to a reference symbol A that denotes each of asynchronous packets transmitted from the nodes 1 to 3 in the cycle time N-A, respectively. Likewise, B1 to B3 and C1 to C3 are added as symbols subsequent to the reference symbol I that denotes each of asynchronous packets transmitted from the nodes 1 to 3 in the cycle time N-B and the cycle time N-C, respectively.
FIG. 3 is a conceptual diagram of the packets transferred onto the serial bus 160 in the conventional communication system. Referring to FIG. 3, an example of timings when packets are transferred onto the serial bus 160 in the conventional technique will be described. As shown in FIG. 3, when the node 1 is designated as a cycle master node, the cycle master 1230 of the node 1 transmits the cycle start request signal to the cycle control circuit 1410 for every 125 μus. In addition, the cycle control circuit 1410 of the node 1 transfers the cycle start packet C to the serial bus 160 to control a cycle time N. During the cycle time N since the cycle start packet C is transferred, a node that acquires a bus control right through arbitration transmits the isochronous packet I onto the serial bus 160. In addition, the asynchronous packet A is transmitted to a designated node by using a free band. For instance, in the cycle time N-A, a cycle start packet C-A and isochronous packets I-A1 to I-A3 are transmitted onto the serial bus 160, and asynchronous packets A-A1 and A-A2 are transmitted to the designated node. In the cycle time N-B, a cycle start packet C-B and isochronous packets I-B1 to I-B3 are transmitted to the serial bus 160, and asynchronous packets A-B1 and A-B2 are transmitted to the designated node. In the cycle time N-C, a cycle start packet C-C and isochronous packets I-C1 to I-C3 are transmitted to the serial bus 160, and asynchronous packets C-C1 and C2 are transmitted to the designated node.
According to the IEEE 1394, the cycle time N is specified as a time in a cycle of 125 μs. Normally, one synchronous packet transmission right is acquired for every cycle. According to the IEEE 1394, therefore, a minimum interval of packet transmission is once for every 125 μs. For this reason, if the node 1 shown in FIG. 2 is to transmit the isochronous packets I-A1 and I-E1, the node 1 needs to transmit the isochronous packet I-A1, to wait for the next cycle packet C-B, and then to transmit the isochronous packet I-B1.
A technique for reducing a delay time resulting from such a cycle time N is disclosed in Japanese Laid Open Patent Publication (JP-P2004-282565A). In this conventional example, a method is disclosed for transmitting packets several times for every 125 μs by giving a procedure of securing a band in synchronous transmission period to an isochronous resource manager (IRM) under the presumption of the IEEE 1394. In the isochronous transmission method of this conventional example, an IEEE 1394-compliant communication device includes the IRM connected to a serial bus and executes the following steps (1) to (7). At the step (1), a time from the start of a cycle to the end of transmission of an isochronous packet is calculated. At the step (2), whenever the node acquires a bandwidth and a channel, a set of the time from the start of the cycle to the end of the transmission of the isochronous packet, the acquired bandwidth, and the acquired channel are stored. At the step (3), the IRM acquires a bandwidth by the end of one request cycle time. At the step (4), it is determined that the request time passes. At the step (5), a channel different from the previously acquired channel is acquired for a next transfer. At the step (6), different channel numbers as many as the number of times of transmitting packets within 125 μs are acquired. At the step (7), an isochronous packet is transmitted with a delay from the cycle start.
According to the IEEE 1394, the cycle time N is specified as 125 μs. Usually, the transmission right of a synchronous packet is given once per one cycle. Thus, in the IEEE 1394, therefore, the minimum interval of packet transmission is 125 μs. For this reason, a maximum delay time of 125 μs is caused. A waiting time up to the cycle time is caused when data is isochronously transmitted, and a transfer delay time is increased. This greatly influences a transfer rate.
In the above conventional isochronous transmission method, the transmission of a plurality of times of synchronous packets within one cycle is permitted. Therefore, it is possible to narrow the minimum interval of packet transfer. However, the synchronous packet transfer time is specified as up to 100 μs according to the IEEE 1394. As a result, it is required that an asynchronous transmission time of 25 μs (=125 μs−100 μs) is necessarily secured, and a time (at least 25 μs) is present during which a band cannot be guaranteed. In this way, the communication system disadvantageously has a long delay time.
For example, in case of a communication system of an imaging device and a data processing device connected to each other by a network, in which system an operation of an operation target is controlled based on a picked-up image data, a transfer rate in the transfer of the image data is an important factor for controlling the operation target. Referring to FIGS. 4A to 4C, the imaging device picks up an image of the operation target within an imaging range, and transfers the picked-up image data of the target to a control device through a network such as an IEEE 1394-compliant network. The control device processes the transmitted image data, and carries out a control such as grasping the operation target and stopping an operation of the target, as in case (1) shown in FIG. 4B. In such a system, if a time (X+Y) necessary for the operation target to pass through the imaging range is shorter than (imaging time)+(data transfer time)+(data processing time)+(control time), the control fails, as in case (2) shown in FIG. 4C. At this time, if a high-speed network is used, an actual data transfer time can be shortened. However, if the cycle time is long, the waiting time for the cycle time is generated, and an advantage of the high-speed network cannot be made use.